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Ethernovia

Technical roles collected by JobSnout, including past vacancies. Tracking since 23 Sept 2026. Last successful scan: 01 Nov 2026. All observation dates are UTC.

This is JobSnout’s recorded coverage, not the company’s complete hiring history. First seen is when we found a posting, not its publication date. “No longer seen” means it disappeared across repeated successful scans; it does not mean someone was hired.

0
Current roles
3
Past roles
3
Roles recorded
0
Reappearances recorded

Roles advertised

3 all roles · newest first · page 1 of 1. Source duplicates are folded into their retained posting.

RoleStatusLocationFirst seenLast seenMarked no longer seen
Senior PLL Design EngineerPythonC++No longer seenUtrecht, The Netherlands23 Sept 202621 Oct 202623 Oct 2026
Senior Analog / Mixed-Signal IC Design EngineerPythonC++No longer seenUtrecht, The Netherlands23 Sept 202621 Oct 202623 Oct 2026
Senior ADC Design EngineerPythonC++No longer seenUtrecht, The Netherlands23 Sept 202621 Oct 202623 Oct 2026

Observed hiring activity

Monthly observations, up to the last 12 months. The initial import can produce a spike. These counts measure postings and reappearances, not hires, headcount growth or unique recruitment campaigns. The current month is incomplete.

Technologies in current roles

Counts are current postings mentioning each technology, not evidence of changes in the company’s stack.

No technology tags recorded for current roles.

Observation timeline

6 recorded events, newest first. Posting updates do not retain historical text versions; role links show the latest stored description.

  1. Marked no longer seenSenior PLL Design Engineer
  2. Marked no longer seenSenior ADC Design Engineer
  3. Marked no longer seenSenior Analog / Mixed-Signal IC Design Engineer
  4. First observedSenior PLL Design Engineer
  5. First observedSenior Analog / Mixed-Signal IC Design Engineer
  6. First observedSenior ADC Design Engineer